Custom Logic

You can implement your own simple logic devices with custom logic chips. (located under "Digital Chips")

Every custom logic device has a model name, which points to a model that describes how it works. You can have any number of devices with the same model. Editing the model changes the behavior of all devices that use that model.

When editing the model, you specify the inputs, the outputs, some info text (which is shown in the lower right corner when hovering the mouse over a device), and the definition.

The inputs (and outputs) is a comma separated list of short pin labels (one or two characters max). You can also specify inverted labels, like /Q for Q. Example: A,B,/C,/D

The definition is multiple lines of the form input=output. The first input pattern that matches the input pins is chosen, and the output pins are set to match the output pattern. The pattern can contain bit values (0, 1), transitions (+, -), wildcards/don't cares (?), and pattern letters (A, B, etc.). The input has to be at least as long as the number of input pins. If it's longer, than the additional pattern characters will be matched against the output pins; this allows you to create devices with state.

The output pattern can also contain _ to indicate a high-impedance state.

Examples:

3 input NAND:

Inputs: A,B,C
Outputs: X
Definition:

111=0
???=1

If all three inputs are 1, the output is 0. Otherwise, it's 1.

Full adder:

Inputs: A,B,C
Outputs: S,C
Definition:

111=11
110=10
011=10
101=10
100=01
010=01
001=01
000=00

SR Latch:

Inputs: S,R
Outputs: Q,/Q
Definition:

?? 00=10
10 ??=10
01 ??=01
?? AB=AB
The input pattern (the left side of the equals sign) matches S, R, Q, and Q, in that order. The right side of the equals sign specifies the resulting Q and Q.

The first line sets the Q output if both outputs are low (this is needed when resetting the circuit). The next line sets the outputs to 1,0 if set is high. The second line sets the outputs to 0,1 if reset is high. The next line keeps the outputs the same otherwise. (The first two letters match the input pins and the second two letters match the output pins. Spaces are ignored, but are added here for clarity.)

D Flip Flop:

Inputs: D,Clk
Outputs: Q,/Q
Definition:

?? 00=10
0+ ??=01
1+ ??=10
?? AB=AB
The first line sets the Q output if both outputs are low (this is needed when resetting the circuit). The next two lines set the Q output to match the D input on a rising transition of the clock. The last line keeps the outputs the same otherwise.

JK Flip Flop:

Inputs: J,K,Clk
Outputs: Q,/Q
Definition:

??? 00=10
00- AB=AB
10- ??=10
01- ??=01
11- AB=BA
??? AB=AB
The first line sets the Q output if both outputs are low (this is needed when resetting the circuit). The next four lines implement the JK flip flop logic on a negative transition of the clock. The last line keeps the outputs the same otherwise.

Digital Comparator:

Inputs: A2,A1,A0,B2,B1,B0
Outputs: Eq,A>,A<
Definition:

ABC ABC=100
1?? 0??=010
A1? A0?=010
AB1 AB0=010
??? ???=001
The first lines checks if the two inputs are equal. The next three lines test if A is larger. Otherwise, B must be larger.

3-Bit Counter:

Inputs: Clk
Outputs: A,B,C
Definition:

+ AB0=AB1
+ A01=A10
+ 011=100
+ 111=000
? ABC=ABC
This counter counts up on positive transition of the Clk input. The first line handles counting up from 000, 010, 100, or 110. The second line handles counting up from 001 or 101. The next two lines handle 011 and 111. The last line ensures that the output doesn't change unless the clock makes a positive transition.

3 input NAND with enable:

Inputs: A,B,C,En
Outputs: X
Definition:

1111=0
???1=1
???0=_

Same as the 3 input NAND above, except that the output goes into a high-impedance state if the enable pin is low.

Tri-state buffer:

Inputs: A,En
Outputs: X
Definition:

A1=A
?0=_

Output is the same as A if the enable bit is high, otherwise it goes into a high-impedance state if the enable pin is low.